fast.waveforms
COMMENT *
This file contains timing waveforms for the SITe 424 2048 x 2048 pixel CCD using the "Right" "B" upper amplifier
Cleaned version Adjusted + commented at Geneva Observatory
*
PAGE 132 ; Printronix page width - 132 columns
CLK2 EQU $002000 ; Clock driver board lower half
CLK3 EQU $003000 ; Clock driver board upper half
VIDEO EQU $000000 ; Video processor board switches
P_DELAY EQU $FF0000 ; Parallel clock delay bits 16-22 320 ns/unit; minimum 140musec ($B00000 avec 3 lignes/state)
PCLR_DE EQU $B00000 ; Same purpose as P_DELAY during the PARALLEL_CLEAR (voodoo timeout with P_DELAY > 3*B00000 ~=46musec)
S_DELAY EQU $080000 ; Serial clock delay bits 16-22 40ns/unit 8*0.04*7*phases=2.24 [musec] or 9.8sec/image
INT_TIM EQU $200000 ; FAST (gain /set=1,..) mode bits 16-21 Dual slope integrator time in 40 nsecs FAST avec 700000 13.3 [musec]/pixel a 400000 9.5 a 100000 5.58 a 100000 5.58
INT_DEL EQU $010000 ; FAST (gain /set=1,..) mode bits 16-21 Dual slope integrator time in 40 nsecs FAST avec 700000 13.3 [musec]/pixel a 400000 9.5 a 100000 5.58 a 100000 5.58
NS_CLR EQU 2068 ; Number of serial clocks to clear (hardware prescan 20+2048 active area)
NP_CLR EQU 2048 ; Number of parallel clocks to clear
SH_DEL EQU 50 ; Shutter delay (electronic shutter)
NP_PSC EQU 20 ; Number of parallel discards per serial clear (AB)
NS_CLRP EQU 1 ; Number of repetion of serial clears to avoid BIAS variation of image (AB)
; Four output video offsets, taken modulo 4096 between 0 and 4095
OFFSET EQU 3305 ; ampli Maire 1/8 offset avec INT_TIM EQU $200000 TIME=0 et PGAIN 2; dBias/dOff=-9.5 offset
OFFSET0 EQU OFFSET
OFFSET1 EQU OFFSET
; CCD clocking voltages
RG_HI EQU 12.0 ; Reset Gate High
RG_LO EQU 0.0
S_HI EQU +7.0 ; Serial High
S_LO EQU -5.0
SW_HI EQU +7.0 ; Summing Well
SW_LO EQU -4.0
P12_HI EQU +4.5 ; Parallel #1 and #2 High
P12_LO EQU -8.5
P3_HI EQU P12_HI+3 ; Parallel #3 High
P3_LO EQU P12_LO+2.0
;P3_LO EQU P12_LO
TG_HI EQU +7.0 ; Transfer Gate High
TG_LO EQU -8.5
;TG_LO EQU -7
ZERO EQU 0.0 ; Unused pins
; DC bias voltages
VOD EQU 24.80 ; Output Drain
VRD EQU 13.40 ; Reset Drain
VLG EQU -3.5 ; Last gate before the summing well
Vmax EQU +12.4 ; Clock driver board rail
; Define switch state bits for the CCD clocks - CLK2, which is the lower bank
RG EQU 1 ; Reset Gate
S1 EQU 2 ; Serial phase #1
S2 EQU 4 ; Serial phase #2
S3 EQU 8 ; Serial phase #3
SW_R EQU $10 ; Summing Well Right
SW_L EQU $20 ; Summing Well Left
; Now for CLK3, which is the upper bank
P1 EQU 1 ; Parallel shift #1
P2 EQU 2 ; Parallel shift #2
P3 EQU 4 ; Parallel shift #3
;P1 EQU 2 ; Parallel shift #1
;P2 EQU 1 ; Parallel shift #2
;P3 EQU 4 ; Parallel shift #3
TG_U EQU 8 ; Transfer Gate Upper
TG_L EQU $10 ; Transfer Gate Lower
SW EQU SW_R+SW_L ; Both summing well are always clocked the
TG EQU TG_U+TG_L ; the same, as are both transfer gates
; ******************************************************
; CLK2+S_DELAY+RG+S1+S2+S3+SW (CLK2)
; CLK3+P_DELAY+P1+P2+P3+TG (CLK3)
; ******************************************************
; Video processor bit definition
; xfer, A/D, integ, Pol+, Pol-, DCrestore, rst (1 => switch open)
; AB: This is used during the idle loop and also 2x at the beginning of the ordinary readout
SERIAL_IDLE
DC END_SERIAL_IDLE-SERIAL_IDLE-1
DC CLK2+S_DELAY+RG+00+S2+S3+00
DC VIDEO+$000000+%1110100 ; Change nearly everything
DC CLK2+S_DELAY+RG+00+00+S3+00
DC CLK2+S_DELAY+00+S1+00+S3+SW
DC CLK2+S_DELAY+00+S1+00+00+SW
DC CLK2+S_DELAY+00+S1+S2+00+SW
DC CLK2+S_DELAY+00+00+S2+00+SW
DC CLK2+S_DELAY+00+00+S2+00+SW ; Dup instead of SXMIT
DC VIDEO+$000000+%1110111 ; Stop resetting integrator
DC VIDEO+$000000+%1110111 ; Additional settling time
DC VIDEO+INT_TIM+%0000111 ; Integrate
DC VIDEO+$000000+%0011011 ; Stop Integrate
DC CLK2+S_DELAY+00+00+S2+00+00 ; Charge dump from summing well
DC VIDEO+$000000+%0011011 ; Delay for signal to settle
DC VIDEO+$000000+%0011011 ; Delay for signal to settle
DC VIDEO+INT_TIM+%0001011 ; Integrate
DC VIDEO+$000000+%0011011 ; Stop integrate, A/D is sampling
END_SERIAL_IDLE
; ******** Right and left are now the same, because B and C are the same *******
; This is lower left readout (C), or upper right through amplifier B (OK)
; Notation B and C sont inverse dans la boite Astromed: C Astromed signifie "right" c.a.d. B
; This is upper right readout, used with amplifier "B" - seule difference par rapp. a "LEFT": $00F041 au lieu $00F000
SERIAL_READ_RIGHT
DC END_SERIAL_READ_RIGHT-SERIAL_READ_RIGHT-1
DC CLK2+S_DELAY+RG+S1+S2+00+00
DC VIDEO+$000000+%1110100 ; Change nearly everything
DC CLK2+S_DELAY+RG+S1+00+00+00
DC CLK2+S_DELAY+00+S1+00+S3+SW
DC CLK2+S_DELAY+00+00+00+S3+SW
DC CLK2+S_DELAY+00+00+S2+S3+SW
DC CLK2+S_DELAY+00+00+S2+00+SW
DC $00F041 ; Transmit A/D #1 data to host
DC VIDEO+$000000+%1110111 ; Stop resetting integrator
DC VIDEO+$000000+%1110111 ; Additional settling time
DC VIDEO+INT_TIM+%0000111 ; Integrate '-' with inverted polarity (offset)
DC VIDEO+$000000+%0011011 ; Stop Integrate
DC CLK2+S_DELAY+00+00+S2+00+00 ; Charge dump from summing well
DC VIDEO+$000000+%0011011 ; Delay for signal to settle
DC VIDEO+$000000+%0011011 ; Delay for signal to settle
DC VIDEO+INT_TIM+%0001011 ; Integrate '+' with non-inverted polarity
DC VIDEO+$000000+%0011011 ; Stop integrate, A/D is sampling
END_SERIAL_READ_RIGHT
SERIAL_SKIP_LEFT ; original Bob
DC END_SERIAL_SKIP_LEFT-SERIAL_SKIP_LEFT-1
DC CLK2+S_DELAY+RG+S1+S2+00+00
DC CLK2+S_DELAY+RG+S1+00+00+00
DC CLK2+S_DELAY+00+S1+00+S3+SW
DC CLK2+S_DELAY+00+00+00+S3+SW
DC CLK2+S_DELAY+00+00+S2+S3+SW
DC CLK2+S_DELAY+00+00+S2+00+00
END_SERIAL_SKIP_LEFT
SERIAL_SKIP_RIGHT ; unused
DC END_SERIAL_SKIP_RIGHT-SERIAL_SKIP_RIGHT-1
DC CLK2+S_DELAY+RG+S1+S2+00+00
DC CLK2+S_DELAY+RG+S1+00+00+00
DC CLK2+S_DELAY+00+S1+00+S3+SW
DC CLK2+S_DELAY+00+00+00+S3+SW
DC CLK2+S_DELAY+00+00+S2+S3+SW
DC CLK2+S_DELAY+00+00+S2+00+00
END_SERIAL_SKIP_RIGHT
SERIALS_CLEAR ; 2.4 [musec/px]
DC END_SERIALS_CLEAR-SERIALS_CLEAR-1 ; meme que SERIAL_READ_LEFT
DC CLK2+S_DELAY+RG+S1+S2+00+00
DC CLK2+S_DELAY+RG+S1+00+00+00
DC CLK2+S_DELAY+00+S1+00+S3+SW
DC CLK2+S_DELAY+00+00+00+S3+SW
DC CLK2+S_DELAY+00+00+S2+S3+SW
DC CLK2+S_DELAY+00+00+S2+00+00
END_SERIALS_CLEAR
; en non-MPP integration sous P3
; Transfer charge up to amplifier C P3-P1-P2; "RIGHT" selon Voodoo broche 14 DB15-static
; one phase of parallel clock [musec]
PARALLEL_UPPER
DC END_PARALLEL_UPPER-PARALLEL_UPPER-1
DC CLK3+P_DELAY+P1+P2+00+00
DC CLK3+P_DELAY+P1+P2+00+00
DC CLK3+P_DELAY+P1+P2+00+00
DC CLK3+P_DELAY+P1+P2+00+00
DC CLK3+P_DELAY+P1+P2+00+00
DC CLK3+P_DELAY+00+P2+00+00
DC CLK3+P_DELAY+00+P2+00+00
DC CLK3+P_DELAY+00+P2+00+00
DC CLK3+P_DELAY+00+P2+00+00
DC CLK3+P_DELAY+00+P2+00+00
DC CLK3+P_DELAY+00+P2+P3+00
DC CLK3+P_DELAY+00+P2+P3+00
DC CLK3+P_DELAY+00+P2+P3+00
DC CLK3+P_DELAY+00+P2+P3+00
DC CLK3+P_DELAY+00+P2+P3+00
DC CLK3+P_DELAY+00+00+P3+TG
DC CLK3+P_DELAY+00+00+P3+TG
DC CLK3+P_DELAY+00+00+P3+TG
DC CLK3+P_DELAY+00+00+P3+TG
DC CLK3+P_DELAY+00+00+P3+TG
DC CLK3+P_DELAY+P1+00+P3+TG
DC CLK3+P_DELAY+P1+00+P3+TG
DC CLK3+P_DELAY+P1+00+P3+TG
DC CLK3+P_DELAY+P1+00+P3+TG
DC CLK3+P_DELAY+P1+00+P3+TG
DC CLK3+P_DELAY+P1+00+00+TG
DC CLK3+P_DELAY+P1+00+00+TG
DC CLK3+P_DELAY+P1+00+00+TG
DC CLK3+P_DELAY+P1+00+00+TG
DC CLK3+P_DELAY+P1+00+00+TG
DC CLK3+P_DELAY+P1+00+00+00
DC CLK3+P_DELAY+P1+00+00+00
DC CLK3+P_DELAY+P1+00+00+00
DC CLK3+P_DELAY+P1+00+00+00
DC CLK3+P_DELAY+P1+00+00+00
END_PARALLEL_UPPER
; Amplifier B/A "LEFT" selon Voodoo; one ligne = 120 microsec with P_DELAY=FF0000 (min spec pour TEK = 100)
; Transfer charge down to amplifier B P3-P2-P1; "LEFT" selon Voodoo
PARALLEL_LOWER
DC END_PARALLEL_LOWER-PARALLEL_LOWER-1
DC CLK3+P_DELAY+00+P2+P3+00 ; Juste, avec la lecture sur ampli B
DC CLK3+P_DELAY+00+P2+P3+00 ; Juste, avec la lecture sur ampli B
DC CLK3+P_DELAY+00+P2+P3+00 ; Juste, avec la lecture sur ampli B
DC CLK3+P_DELAY+00+P2+00+00
DC CLK3+P_DELAY+00+P2+00+00
DC CLK3+P_DELAY+00+P2+00+00
DC CLK3+P_DELAY+P1+P2+00+00
DC CLK3+P_DELAY+P1+P2+00+00
DC CLK3+P_DELAY+P1+P2+00+00
DC CLK3+P_DELAY+P1+00+00+TG
DC CLK3+P_DELAY+P1+00+00+TG
DC CLK3+P_DELAY+P1+00+00+TG
DC CLK3+P_DELAY+P1+00+P3+TG
DC CLK3+P_DELAY+P1+00+P3+TG
DC CLK3+P_DELAY+P1+00+P3+TG
DC CLK3+P_DELAY+00+00+P3+TG
DC CLK3+P_DELAY+00+00+P3+TG
DC CLK3+P_DELAY+00+00+P3+TG
DC CLK3+P_DELAY+00+00+P3+00
DC CLK3+P_DELAY+00+00+P3+00
DC CLK3+P_DELAY+00+00+P3+00
END_PARALLEL_LOWER
; utilise avec PARALLEL_UPPER
PARALLEL_CLEAR ; utilise par voodoo lors du "idle" et "clear" a commenter/decommenter selon le choix de l'ampli
DC END_PARALLEL_CLEAR-PARALLEL_CLEAR-1
DC CLK3+PCLR_DE+P1+P2+00+00 ; Juste, avec la lecture sur ampli C
DC CLK3+PCLR_DE+P1+P2+00+00
DC CLK3+PCLR_DE+P1+P2+00+00
DC CLK3+PCLR_DE+00+P2+00+00
DC CLK3+PCLR_DE+00+P2+00+00
DC CLK3+PCLR_DE+00+P2+00+00
DC CLK3+PCLR_DE+00+P2+P3+00
DC CLK3+PCLR_DE+00+P2+P3+00
DC CLK3+PCLR_DE+00+P2+P3+00
DC CLK3+PCLR_DE+00+00+P3+TG
DC CLK3+PCLR_DE+00+00+P3+TG
DC CLK3+PCLR_DE+00+00+P3+TG
DC CLK3+PCLR_DE+P1+00+P3+TG
DC CLK3+PCLR_DE+P1+00+P3+TG
DC CLK3+PCLR_DE+P1+00+P3+TG
DC CLK3+PCLR_DE+P1+00+00+TG
DC CLK3+PCLR_DE+P1+00+00+TG
DC CLK3+PCLR_DE+P1+00+00+TG
DC CLK3+PCLR_DE+P1+00+00+00
DC CLK3+PCLR_DE+P1+00+00+00
DC CLK3+PCLR_DE+P1+00+00+00
END_PARALLEL_CLEAR
DACS DC END_DACS-DACS-1
DC $0A0080 ; DAC = unbuffered mode
DC $200100+@CVI((RG_HI+Vmax)/(2*Vmax)*255) ; Pin #1, Reset Gate
DC $200200+@CVI((RG_LO+Vmax)/(2*Vmax)*255)
DC $200400+@CVI((S_HI+Vmax)/(2*Vmax)*255) ; Pin #2, Serial #1
DC $200800+@CVI((S_LO+Vmax)/(2*Vmax)*255)
DC $202000+@CVI((S_HI+Vmax)/(2*Vmax)*255) ; Pin #3, Serial #2
DC $204000+@CVI((S_LO+Vmax)/(2*Vmax)*255)
DC $208000+@CVI((S_HI+Vmax)/(2*Vmax)*255) ; Pin #4, Serial #3
DC $210000+@CVI((S_LO+Vmax)/(2*Vmax)*255)
DC $220100+@CVI((SW_HI+Vmax)/(2*Vmax)*255) ; Pin #5, Summing well Right
DC $220200+@CVI((SW_LO+Vmax)/(2*Vmax)*255)
DC $220400+@CVI((SW_HI+Vmax)/(2*Vmax)*255) ; Pin #6, Summing well Left
DC $220800+@CVI((SW_LO+Vmax)/(2*Vmax)*255)
DC $222000+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #7, Unused
DC $224000+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $228000+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #8, Unused
DC $230000+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $240100+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #9, Unused
DC $240200+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $240400+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #10, Unused
DC $240800+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $242000+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #11, Unused
DC $244000+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $248000+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #12, Unused
DC $250000+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $260100+@CVI((P12_HI+Vmax)/(2*Vmax)*255) ; Pin #13, Parallel #1
DC $260200+@CVI((P12_LO+Vmax)/(2*Vmax)*255)
DC $260400+@CVI((P12_HI+Vmax)/(2*Vmax)*255) ; Pin #14, Parallel #2
DC $260800+@CVI((P12_LO+Vmax)/(2*Vmax)*255)
DC $262000+@CVI((P3_HI+Vmax)/(2*Vmax)*255) ; Pin #15, Parallel #3
DC $264000+@CVI((P3_LO+Vmax)/(2*Vmax)*255)
DC $268000+@CVI((TG_HI+Vmax)/(2*Vmax)*255) ; Pin #16, Transfer Gate Upper; required HI for OUT B, LO for OUT C
DC $270000+@CVI((TG_LO+Vmax)/(2*Vmax)*255)
DC $280100+@CVI((TG_HI+Vmax)/(2*Vmax)*255) ; Pin #17, Transfer Gate Lower; required HI for OUT C, LO for OUT B
DC $280200+@CVI((TG_LO+Vmax)/(2*Vmax)*255)
DC $280400+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #18, Unused
DC $280800+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $282000+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #19, Unused
DC $284000+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $288000+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #33, Unused
DC $290000+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $2A0100+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #34, Unused
DC $2A0200+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $2A0400+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #35, Unused
DC $2A0800+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $2A2000+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #36, Unused
DC $2A4000+@CVI((ZERO+Vmax)/(2*Vmax)*255)
DC $2A8000+@CVI((ZERO+Vmax)/(2*Vmax)*255) ; Pin #37, Unused
DC $2B0000+@CVI((ZERO+Vmax)/(2*Vmax)*255)
; Set gain and integrator speed. (77, bb, dd, ee; low gain to high 1,2,5,10 fxx = speed 1, cxx 0)
; DC $0c3f77 ; x1 = Low gain, fast integrate
; DC $0c3cbb ; x1 Gain, slow integrate
; DC $0c3cee ; x2 Gain, slow integrate
DC $0c3fbb ; gain=2, time-constant 1 (fast)
; Output offset voltages to get about 1000 ADUs on a bias frame
DC $0c8000+OFFSET0 ; Output video offset, Output C
DC $0cc000+OFFSET1 ; Output video offset, Output B
; DC bias supply voltages
DC $0d0000+@CVI((VOD-7.5)/22.5*4095) ; Output Drain, pin #1
DC $0c0000+@CVI((VRD-5.0)/15.0*4095) ; Reset Drain, pin #3
DC $0e0000+@CVI((VLG+10.0)/20.0*4095) ; Last Gate, pin #9
END_DACS
; Check for overflow in the EEPROM case
IF @SCP("DOWNLOAD","EEPROM")
IF @CVS(N,@LCV(L))>(APL_NUM+1)*N_W_APL
WARN 'EEPROM overflow!' ; Make sure the next application
ENDIF ; will not be overwritten
ENDIF